A 10-bit 160-MSPS 2.5-V Segmented Current Steering CMOS DAC for WLAN Applications
نویسندگان
چکیده
This paper presents a 10-bit 160-MSPS 2.5-V digital to analog converter (DAC) and is implemented in TSMC 0.25μm CMOS technology. A segmented current steering architecture is used with optimized performance for speed, resolution, power consumption and area. The DAC can be operated up to 160MHz sampling frequency and the settling time is less than 4.8 ns. The differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.3 and ±0.4 least significant bits (LSBs), respectively. The spurious free dynamic range (SFDR) at 160-MSPS remains above 68 dB for input frequency up to 50 MHz. Total power dissipation is 45.3 mW with 2.5-V power supply. The chip size is 1.73 mm × 1.2 mm.
منابع مشابه
Sr No Area Page No 1 Microelectronics , VLSI & Display Technology 11 - 26 2 RF Microwaves & Photonics 27 - 36 3 Signal Processing , Communications & Networks 37 - 74 4 Power and Control 75 - 92
A 10 bit current steering CMOS digital-to-analog converter (DAC) is designed, with optimized performance for frequency domain applications. To get the best of both binary-weighted and thermometer-coded architectures, most current-steering D/A converters are implemented using a segmented architecture. Segmentation is chosen to reduce the total area occupied by the DAC. The optimum segmentation f...
متن کاملA Self-calibrating current-steering 12-bit DAC based on new 1-bit self-test scheme
This paper presents a self-test self-correction scheme for segmented current steering (CS) DACs. Prior art is critically analyzed. The new scheme improves the DAC linearity by improving the accuracy of the thermometer current sources. The algorithm, which controls the scheme, is described in details. A 12-bit CS DAC, with 6-6 segmentation, is implemented using the new scheme and algorithm. The ...
متن کامل10-bit segmented current steering DAC in 90nm CMOS technology
This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area ...
متن کاملAn On-Chip DNL Estimation Technique and Reconfiguration for Improved Linearity in Current Steering Digital to Analog Converters
This paper proposes a reconfigurable current steering digital to analog converter (DAC). The differential non-linearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). A 10 bit segmented DAC along with the associated circuits for DNL estimation was designed and fabricated using 0.35μm CMOS technolo...
متن کاملAn 8 bit current steering DAC for offset compensation purposes in sensor arrays
An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current ...
متن کامل